1. Field of the Disclosure
This disclosure relates generally to formal verification of circuit designs, and more specifically to formal verification coverage metrics for formal verification of circuit designs.
2. Description of Related Art
Over the last 30 years, the complexity of integrated circuits has increased greatly. This increase in complexity has exacerbated the difficulty of verifying circuit designs. In a typical integrated circuit design process, which includes many steps, the verification step consumes approximately 70-80% of the total time and resources. Aspects of the circuit design such as time-to-market and profit margin greatly depend on the verification step. As a result, flaws in the design that are not found during the verification step can have significant economic impact by increasing time-to-market and reducing profit margins.
As the complexity in circuit design has increased, there has been a corresponding improvement in various kinds of verification and debugging techniques. In fact, these verification and debugging techniques have evolved from relatively simple transistor circuit-level simulation (in the early 1970s) to logic gate-level simulation (in the late 1980s) to the current art that uses Register Transfer Language (RTL)-level simulation. RTL describes the registers of a computer or digital electronic system and the way in which data are transferred among them.
Existing verification and debugging tools are used in the design flow of a circuit. The design flow begins with the creation of a circuit design at the RTL level using RTL source code. The RTL source code is specified according to a Hardware Description Language (HDL), such as Verilog HDL or VHDL. Circuit designers use high-level hardware description languages because of the size and complexity of modern integrated circuits. Circuit designs are developed in a high-level language using computer-implemented software applications, which enable a user to use text-editing and graphical design tools to create a HDL-based design.
In the design flow, creation of the RTL source code is followed by verification of the design to check if the RTL source code meets various design specifications. Formal verification is one such technique for verifying the circuit design. Formal verification uses mathematical techniques to prove that, under a set of constraints, a design property is either always true or to provide an example condition (called a counterexample) that demonstrates the property is false. Tools that use formal methods to verify RTL source code and design properties are known as “model checkers.” Design properties to be verified include specifications and/or requirements that must be satisfied by the circuit design. Since mathematical properties define the design requirements in pure mathematical terms, this enables analysis of all possible valid inputs for a given circuit and is akin to an exhaustive simulation.
Due to mathematically complex nature of formal analysis, it is possible that the computation may hit resource limits, such as time and available memory. An incomplete formal analysis can be measured in terms of number of cycles the analysis of the design has gone through. When formal analysis is incomplete, it is useful to know how much of the possible reachable state space has been covered during the formal verification before the resource limit was reached. However, establishing that measure is not practical since determining the exact reachable state space is itself a hard problem.